Conventionally, there is this kind of reconfiguration controlling apparatus for the optically reconfigurable gate array as disclosed in JP-2002-353317 A (which is referred to as Patent Document 1 hereinafter), JP-2005-051059 A (which is referred to as Patent Document 2 hereinafter) and Article “Improvement of Reconfiguring Speed of ODRGA Using Plural VSSEL's by Motoji Miyano, Minoru Watanabe and Fuminori Kobayashi” in the Institute of Electronics, Information and Communication Engineers (which is referred to as Non-Patent Document 1). FIG. 12 shows a schematic arrangement view of the reconfiguration controlling apparatus for the optically reconfigurable gate array, as disclosed in the aforesaid Patent Documents 1 and 2; FIG. 13 shows an operational flowchart of the reconfiguration controlling apparatus for the optically reconfigurable gate array, as disclosed in the aforesaid Patent Documents 1 and 2; and FIG. 14 shows a prior art schematic arrangement view of the aforesaid. Non-Patent Document 1.
In an arrangement of the reconfiguration controlling apparatus for the optically reconfigurable gate array according to the invention disclosed in the aforesaid Patent Document 1, when an optical reconfiguration type gate array 3, in which logical arithmetic operation cells and light receiving elements for setting an arithmetic program to the logical arithmetic operation cells are mounted on a planar chip, is reconfigured, a hologram memory 2 serving as an optical memory means, which is opposed to the optical reconfiguration type gate array 3, is irradiated with laser lights 1a to thereby emit reproduction lights therefrom, and the reproduction lights are simultaneously projected on the light receiving elements of the optical reconfiguration type gate array 3 as a light pattern 2a of optical signals according to the arithmetic program.
Like this, by simultaneously projecting the light pattern 2a of the optical signals on the plurality of light receiving elements mounted on the planar chip of the optical reconfiguration type gate array 3, it is possible to reconfigure the logical arithmetic operation cells of the optical reconfiguration type gate array 3 as a logical arithmetic operation circuit.
Also, the reconfiguration controlling apparatus for the optically reconfigurable gate array according to the invention disclosed in Patent Document 2 includes a hologram memory 2 serving as an optical memory means, which is placed above an upper surface of an optically reconfigurable gate array 3, a laser array 1 such as a planar light emission laser, which serves as a reproduction-light-causing irradiation means, to thereby irradiate the hologram memory 2 with laser lights 1a serving as reproduction-light-causing irradiation lights, and a reproduction-light-causing irradiation control means 4 such as a reproduction-light-causing irradiation control circuit for controlling the laser lights 1a of the laser array 1, which serve as the reproduction-light-causing irradiation lights.
The laser array 1 is a light source for generating the reproduction-light-causing irradiation lights to reproduce a piece of information regarding the optical pattern 2a which is recorded in the hologram memory 2. An irradiation angle control section 50 is provided on an irradiation face of the laser array 1 to control an irradiation angle of the reproduction-light-causing irradiation lights to the hologram memory 2. The irradiation angle of the laser lights 1a serving as the reproduction-light-causing irradiation lights is varied over time in synchronization with an operation of the optical reconfiguration type gate array 3. A control of the irradiation angle of the laser lights la, i.e., the reproduction-light-causing irradiation lights, is carried out by controlling the irradiation angle control section 50 with the reproduction-light-causing irradiation control means 4.
The laser lights 1a serving as the reproduction-light-causing irradiation lights, with which the hologram memory 2 is irradiated by the laser array 1, pass through the hologram memory 2 so as to be transformed into the optical pattern 2a of reproduction lights. Namely, a mask pattern, which is recorded as a hologram in the hologram memory 2, is reproduced, and the reproduced lights define the optical pattern 2a. Then, the optical pattern 2a is projected on the optical reconfiguration type gate array 3. The optical reconfiguration type gate array 3 carries out a photoelectric conversion to the optical pattern 2a to thereby reconfigure a logical arithmetic operation circuit in correspondence to the optical pattern 2a. 
Next, an operation of the reconfiguration controlling apparatus for the optically reconfigurable gate array as disclosed in the aforesaid Patent Documents 1 and 2 will now be explained on the basis of FIG. 13. In this drawing, when it is determined that a boot-up signal of the reconfiguration controlling apparatus for the optically reconfigurable gate array is input to the reproduction-light-causing irradiation control means 4 (step 11), the reproduction-light-causing irradiation control means 4 outputs a light emission control signal S41 to the laser array 1 (step 12). The light emission control signal S41 is constituted so as to have a data content of a reconfiguring time which is set as the maximum reconfiguring time which is required of one of logical arithmetic operation circuits to be reconfigured by the hologram memory 2.
The laser array 1, to which the aforesaid light emission control signal S41 is input, emits laser lights 1a according to the reconfiguring time specified by the light emission control signal S41, and the hologram memory 2 is irradiated with the emitted laser lights 1a (step 13). Due to the irradiation of the hologram memory 2 with the laser light 1a, the hologram memory 2 projects an optical pattern 2a on the optical reconfiguration type gate array 3 based on a piece of record information previously stored therein (step 14).
The reproduction-light-causing irradiation control means 4 counts a projection time of the optical pattern 2a from the start of the projection of the optical pattern 2a (step 15), and then it is determined whether the counted projection time has exceeded the maximum value among the optical reconfiguring times which is set by the light emission control signal S41 (step 16). When it is determined that the counted projection time has not exceeded the maximum value, the control returns to step 13, and then the routine comprising the steps concerned is repeated.
At step 16, when it is determined that the counted projection time has exceeded the maximum value, a logical arithmetic operation circuit on the optical reconfiguration type gate array 3, which corresponds to the reconfigured circuit pattern concerned, is driven, and a logical arithmetic operation is executed upon inputting input data S1 to the driven logical arithmetic operation circuit, so that output data S2 is output as a result of the logical arithmetic operation from the optical reconfiguration type gate array 3 (step 17). Then, it is determined whether the logical arithmetic operation concerned has been completed in the driven logical arithmetic operation circuit (step 18). When it is determined that the logical arithmetic operation has been completed, it is further determined whether all logical arithmetic operations have been completed in logical arithmetic operation circuits, which would be optically reconfigured by the reproduction-light-causing irradiation control means 4 (step 19). At step 19, when it is determined that all the logical arithmetic operations have not been completed, the control returns to step 12, and then the routine comprising the steps concerned is repeated to optically reconfigure a next logical arithmetic operation circuit.
The projection of an optical pattern 2a is carried out over the sufficient period of time, during which each of all logical arithmetic operation circuits can be reconfigured in the optical reconfiguration type gate array 3, i.e., over the reconfiguring time which is set by the light emission control signal S41.
On the other hand, the invention described in Non-Patent Document 1 has an arrangement in which laser light beams are emitted from two planar emission lasers 21 and 22 defining a quasi hologram memory 2, and are made incident on an optical reconfiguration type gate array 3 formed by a single VLSI, through the intermediary of an optical system 23, thereby carrying out an optical reconfiguration. With this arrangement, it is possible to improve a reconfiguring speed because photodiodes on the optical reconfiguration type gate array 3 can be illuminated with a large amount of laser light.
In the invention having the above-mentioned arrangement, the optical reconfiguration type gate array 3 is defined as the VLSI having an 4-bit up/down counter mounted thereon. A case where the 4-bit up/down counter was driven with the irradiation using only the single planar emission laser 21 (or 22) was compared with a case where the 4-bit up/down counter was driven with the irradiation using both the planar emission lasers 21 and 22. When only the single planar emission laser 21 (or 22) was used, the counted value was 580 [μ sec.] (or 1340 [μ sec.]). In contrast, when both the planar emission lasers 21 and 22 was used, the counted value was 340 [μ sec.]. It was confirmed that the optical reconfiguring speed could become higher when both the planar emission lasers 21 and 22 was used.
In each of the above-mentioned reconfiguration controlling apparatuses for the optical reconfiguration type gate array, it is possible to carry out a highly quick writing in parallel in the VLSI of the optically reconfigurable gate array 3, and there is an advantage that the hologram memory 2 can store a large number of circuit patterns to be reconfigured (for example, on the order of 100).                Patent Document 1: JP-2002-353317 A        Patent Document 2: JP-2005-051059 A        Non-Patent Document 1: Article “Improvement of Reconfiguring Speed of ODRGA Using Plural VSSEL's by Motoji Miyano, Minoru Watanabe and Fuminori Kobayashi” in the Institute of Electronics, Information and Communication Engineers        